This invention relates to a semiconductor memory device having a specific circuit construction for a test and a method of testing the same.
For checking the quality of a plurality of memory cells, various tests such as SCAN, MARCHING are conducted in not only general purpose semiconductor memory devices such as SRAM, DRAM but also on-chip type semiconductor memory devices in which a memory circuit is built on a same chip as a processor.
As to the SCAN widely known as an essential test, a non-inverse pattern of test data, namely, ALL "0"s is applied so that "0" is sequentially written into all memory cells. Then, the data held In respective memory cells are sequentially read out to check whether the read-out data conform with an expected value "0". In case where unconformity is detected in any of the memory cells, the test results in FAIL at that time. In case where the conformity is obtained in every memory cell, an inverse pattern of test data, namely, ALL "1"s is applied so that "1" is sequentially written into all memory cells. Then, the data held in respective memory cells are sequentially checked whether the data conform with an expected value "1". In case only where the conformity is obtained in every memory cell, the test results in PASS.
As to the MARCHING, the non-inverse pattern of test data (ALL "0"s) is applied so that the test data "0" is sequentially written into all the memory cells similarly to the SCAN. Then, the data held In the memory cell of the first address is read out to check whether the data conforms with the expected value "0". In case where the unconformity is detected in the memory cell the test results in FAIL at that time. In case where the conformity is obtained in the memory cell, "1" is written into the memory cell of the first address and checked is whether the data held in the memory cell of the second address conforms with the expected value "0". In case where the conformity is obtained in the second address memory cell, "1"is written into the second address memory cell and checked is whether the data held in the third address memory cell conforms with the expected value "0". Each memory cell is checked sequentially until the data held in all memory cells are rewritten into "l" in such a manner. This is a forward process for the non-inverse pattern. Then a backward process for the same pattern is executed. In detail, sequentially from the memory cell of the final address, while checking whether a read-out data conforms with the expected value "1", "0"is written into the memory cells. The sequential judgment to each memory cell is executed until the data held in all memory cells are returned to "0". Further, the inverse pattern of test data (ALL "1"s) is applied and similar forward/backward processes are executed.
As described above, in case of a semiconductor memory device having N memory cells to which addresses are differently allocated From one another, memory accesses of 2N.times.2 times in the SCAN and 5N.times.2 times in the MARCHING are respectively required. The test which requires such memory accesses of multiple times of N is commonly called N-system test.
Recently, semiconductor memory devices have been increasing in their memory capacity. For example, the capacity of general purpose semiconductor memory devices has been developed to 1M bits, 4M bits or 16M bits in SRAMs and to 4M bits, 16M Bits or 64M bits in DRAMs and is further being increased. On-chip type semiconductor memory devices are also promoted to increase their memory capacity.
Suppose that a time required for one memory access (operation cycle time) T is 100 ns, in the semiconductor memory device with 4M.times.1-bit memory construction (N=4M bits), a total test time in the SCAN (2N.times.2.times.T) rows to about 1.6 s and that of the MARCHING (5N.times.2.times.T) grows to about 4.0 s Accompanied by the increase in the memory capacity, it is hard to ignore the time required for executing the memory test even in case of the N-system test.
Conventionally, N.sup.1.5 -system test or N.sup.2 -system test is applied for enhancing an error detecting rate. It is practically difficult, however, to perform tests other than the N-system test as long as the conventional method is adopted. In case of the N.sup.2 -system test which requires, for example, 4N.sup.2 times memory accesses, under the same condition (N=4M bits, T=100ns), the total test time (4N.sup.2 .times.T) is about 6.4.times.10.sup.6 s (about 74 days). Usually discussed is a cost for test time in a level of a Few seconds, thus such the value is out of discussion.
In view of the above problem, as one of techniques for reducing the test time, a merged match-line test method is proposed in "A 45 ns 64 Mb DRAM with a Merged Match-line Test Architecture", Mori, S., et al., IEEE ISSCC Digest of Technical Papers, page 110-111, February, 1991. In this method, a plurality of memory cells connected to one word line are tested at one time. Further, wires used as a pair of data output lines during a normal read-out operation are used as a pair of match lines during the test.
In the merged match line test method, however, data are read out to the pair of match lines by activating one word line, therefore the method can be applied only to a test per one word. The reduction of test time is thus restricted. Moreover, since the construction is such that the pair of match lines are both precharged simultaneously and an error detection can be carried out only when both lines are in an electric potential of "L", an electric current is conducted through one of the pair of match lines even when no memory errors exist, thus increasing an consumptive electric current during the test.
The present invention has its object to reduce the test time to the minimum. Another object of the present invention is to lower the consumptive electric current during the test.